But technically, it has one more core in SMT8 mode or two more cores in SMT4 mode (which have 4 MB of associated 元 cache).

To improve the yield of chips on the 7 nanometer process, IBM is figuring that at least one SMT8 core and its 8 MB 元 region is going to be a dud, and thus it is calling Power10 a 15-core SMT8 chip. If they are pinning a VM to a core.Īs you can see from the die above, there are 16 physical cores in SMT8 mode on the Power10 die, which is the version IBM was showing off at Hot Chips, but clearly there would be 32 physical cores in SMT4 mode. IBM will dial the SMT4 or SMT8 cores and set them based on specific customer needs, as it has done with Power8 and Power9 before it, with SMT8 cores used for commercial workloads and SMT4 being used for HPC, hyperscaler, and cloud customers for the most part where they want as many VMs per machine as possible. The fact that users cannot change the mode means that IBM and its third party software suppliers know what to charge per core. While we strongly suspect that IBM has designed a single chip to operate in either mode, this mode is set in the hardware itself and is not resettable by itself or by end users. The Power10 chip will come in versions that support either cores with eight threads per core (SMT8 in the IBM lingo) or twice as many cores with four threads per core (SMT4 mode). What we do know is that IBM went with a clean sheet resign of the Power10 core, which Thompto confirmed, and what we can see from the die that IBM pushed the limits a bit more thanks to the fact that is has 18 billion transistors to play with in a 602 square millimeter die. Somewhere along the way – probably between when GlobalFoundries spiked its 7 nanometer efforts in August 2018 and when it said publicly it was moving to Samsung as its foundry for Power10 – we think Big Blue went with a more aggressive plan. Take a look:Īs we told you last week, the original plan for Power10 seemed to be to create an updated 24-core processor based generally on the Power9 design and then put two of these chips into a single socket to boost it to 24 cores with the process shrink from 14 nanometers at the GlobalFoundries fab to its 7 nanometer extreme ultraviolet (EUV) technologies. Let’s start at the die level and work our way inside. (That’s lame, and we are having none of that. Or will any time soon.īut this week, let’s get into the Power10 chip itself, which we have nicknamed “Cirrus” because IBM did not give it a cool codename, apparently. (The pieces were all there, and I felt it in the cosmic ether, I guess.) This memory clustering is evolutionary as far as IBM is concerned, being based on shared memory ideas it has had in the AS/400 line as well as supercomputers over the decades, but it is revolutionary as far as the industry is concerned because no one else has anything like this. This last bit is the neat bit – and something I have been ruminating about in recent weeks at The Next Platform without knowing that IBM was in fact working on this. And finally, and enthusiastically, we will take a deep look at a new cross-system memory clustering technology that will prove to be pivotal in the use of Power10 processing in clouds and perhaps in all kinds of distributed computing. In the next few weeks, we will be peeling off the technology layers of Power10, looking at the processor architecture and design itself, the system designs Power10 engenders, the expected performance of the Power10 chip relative to Power7, Power8, and Power9. And we know a lot of chipheads, and generally, they are good folk doing the hard job of engineering in a tough environment. IBM may have its issues, but these people are still among the best in the world. The entire Power10 team needs to be congratulated on creating a fine processor and an even more interesting system architecture. A bunch of other Power Systems people have given us insight on the new chip, including Steve Sibley, vice president and offering manager for the Cognitive Systems division. The presentation at Hot Chips was given by William Starke, the chief architect of the Power10 processor who has helped steer several generations of Power chips from IBM (along with many others), and Brian Thompto, the Power10 core architect who was given the job of starting from scratch with the Power10 core with a focus on energy efficiency. And this week, we can drill down into the Power10 architectural details a bit more. IBM was gracious enough to let us talk about the Power10 chip generally before that presentation, because we have a Monday morning deadline no matter what. Last week, we told you some general things about the future Power10 chip from IBM based on a roadmap briefing that we got from the IBM tech team ahead of their presentation at the Hot Chips 32 chip conference last week. Drilling Down Into The Power10 Chip Architecture

Power9 cpu transistor switch